1. Field of the Invention
The present invention relates to an inverter circuit. More particularly, the present invention relates to an inverter circuit driving a backlight for a liquid crystal display.
2. Description of the Related Art
A cold cathode fluorescent lamp (“CCFL”) is widely used as a backlight for a liquid crystal display. The CCFL has two terminals and emits light when an alternating current voltage having a few thousand volts is applied to the two terminals. However, a direct current voltage is required to drive the liquid crystal display, while an alternating current voltage of 100 volts˜220 volts is applied from an exterior. Thus, the alternating current voltage from the exterior is converted into a direct current voltage. An inverter transformer in the liquid crystal display is driven by the direct current voltage inputted through a primary winding thereof and outputs a boosted alternating current voltage through a secondary winding thereof to drive the CCFL.
The inverter circuit is used to drive the primary winding of the inverter transformer and has a low-voltage field effect transistor (“FET”) and a high-side FET that are electrically connected between a ground and a direct current voltage terminal in parallel. The high-side FET and the low-side FET are alternately turned on.
For example, an inverter circuit having the low-side FET and the high-side FET is disclosed in Japanese Laid-Open Patent Application 2001-136749. However, the high-side FET and the low-side FET of the inverter circuit disclosed in the Japanese Laid-Open Patent Application 2001-136749 have a different polarity from each other. That is, the low-side FET is an N-channel type FET, while the high-side FET is a P-channel type FET. As is well known, the P-channel type FET uses holes having a lower mobility than electrons of the N-channel type FET. As a result, the P-channel type FET is not suitable for a high-speed switching environment and has a lower driving capability than that of the N-channel type FET. Therefore, the P-channel type FET is not used for a high voltage of about 500 volts.
FIG. 1 is a circuit schematic diagram showing a conventional inverter circuit employing an N-channel type FET as the low-side FET and the high-side FET. FIG. 2 is a waveform diagram showing gate voltages of the N-channel type FETs shown in FIG. 1.
Referring to FIG. 1, first and second control signal generating circuits 1001 and 1002, respectively, output square pulses that are complementary to each other and do not overlap each other. Outputs of the first and second control signal generating circuits 1001 and 1002 are connected to primary windings of first and second driving transformers 1003 and 1004, respectively. A power voltage circuit 1005 generates a direct current voltage. An N-channel type field effect transistor (an N-channel type FET) 1006 for a high voltage and an N-channel type FET 1007 for a low voltage are connected between the power voltage circuit 1005 and a ground. A node between the high-side FET 1006 and the low-side FET 1007 is defined as a driving node 1006a. The high-side FET 1006 has a gate connected to a secondary winding of the first driving transformer 1003 and the low-side FET 1007 has a gate connected to a secondary winding of the second driving transformer 1004. The driving node 1006a between the high-side FET 1006 and the low-side FET 1007 is connected to a primary winding of an inverter transformer 1008, and a secondary winding of the inverter transformer 1008 is connected to cold cathode fluorescent lamps (CCFLs, not shown). A capacitor 1011 is connected between the first driving transformer 1003 and the gate of the high-side FET 1006, a capacitor 1012 is connected between the second driving transformer 1004 and the gate of the low-side FET 1007, and a capacitor 1013 is connected between the driving node 1006a and the primary winding of the inverter transformer 1008.
In general, the inverter circuit shown in FIG. 1 includes a first clamp circuit 1009 connected between the gate of the high-side FET 1006 and a source of the high-side FET 1006 (driving node 1006a) and a second clamp circuit 1010 connected between the gate of the low-side FET 1007 and a source of the low-side FET 1007 (ground 1007a).
The inverter circuit shown in FIG. 1 is operated as follows.
When the first and second control signal generating circuits 1001 and 1002 generate the square pulses, the square pulses are applied to the secondary windings of the first and second driving transformers 1003 and 1004, respectively. As a result, the high-side FET 1006 and the low-side FET 1007 are alternately turned on and the power voltage from the power voltage circuit 1005 and the ground voltage from the ground 1007a are alternately applied to the driving node 1006a. That is, an alternating current having an amplitude between the power voltage and the ground voltage is applied to the primary winding of the inverter transformer 1008. The inverter transformer 1008 outputs a boosted alternating current in response to the alternating current through the secondary winding thereof to drive the CCFLs.
The first and second clamp circuits 1009 and 1010 are employed to apply a positive voltage to the high-side FET 1006 and the low-side FET 1007, respectively.
However, a conventional transformer has a parasitic capacitance between primary and secondary windings thereof, and the parasitic capacitance causes many problems.
As shown in FIG. 2, the gate voltage of the high-side FET 1006 (a potential difference between the source and the gate of the high-side FET 1006) and the gate voltage of the low-side FET 1007 (a potential difference between the source and the gate of the low-side FET 1007) are not lowered below a predetermined negative voltage due to the first and second clamp circuits 1009 and 1010. The gate of the high-side FET 1006 receives a positive square pulse applied from the first driving transformer 1003 and the gate of the low-side FET 1007 also receives a positive square pulse applied from the second driving transformer 1004. When the low-side FET 1007 is turned on, the voltage level at the driving node 1006a is rapidly lowered to the ground voltage level. However, due to the parasitic capacitance, the gate voltage level of the high-side FET 1006 does not easily follow the lowering of the source thereof. As a result, the gate voltage of the high-side FET 1006 has the positive voltage level momentarily, so that the high-side FET 1006 is turned on. Thus, since the low-side FET 1007 is already turned on when the high-side FET 1006 is momentarily turned on, a shoot-through current flows through the high-side FET 1006 and the low-side FET 1007 due to the parasitic capacitance.
As a result, an output voltage level of the power voltage circuit 1005 is varied when the power voltage circuit 1005 generates the direct current voltage and the high-side FET 1006 and the low-side FET 1007 are overheated. Thus, the efficiency of the FETs 1006 and 1007 is deteriorated, thereby increasing power consumption.